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Job title
Full-time Designer — Verilog / VHDL Specialist (Ref 6101)
DescriptionLooking for talent to help us support in verilog / vhdl specialist. You will work with a small, focused team. Clear communication and documentation are important. Expected duration: 6 weeks. Budget tag: $150-5. Apply with a short note on your availability; include 1-2 relevant examples. Skill match score (0-9): 4/9. We review submissions in batches.
Posted byAditya GuptaCountryIndiaPosted on3 Aug 2026
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